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independent clock hotlink ii? serializer and reclocking deserialize r CYV15G0104TRB cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-02100 rev. *b revised july 8, 2005 features ? second-generation hotlink ? technology ? compliant to smpte 292 m and smpte 259m video standards ? single channel video serializer plus single channel video reclocking deserializer ? 195- to 1500-mbps serial data signaling rate ? simultaneous operation at different signaling rates ? supports reception of either 1.485 or 1.485/1.001 gbps data rate with the same training clock ? internal phase-locked loops (plls) with no external pll components ? supports half-rate and full-rate clocking ? selectable differential pecl-compatible serial inputs ? internal dc-restoration ? redundant differential pecl- compatible serial outputs ? no external bias resistors required ? internal source termination ? signaling-rate controlled edge-rates ? synchronous lvttl parallel interface ? jtag boundary scan ? built-in self-test (bist) for at-speed link testing ? link quality indicator ? analog signal detect ? digital signal detect ? low-power 1.8w @ 3.3v typical ? single 3.3v supply ? thermally enhanced bga ? pb-free package option available ?0.25 bicmos technology functional description the CYV15G0104TRB independent clock hotlink ii? serializer and reclocking deserializer is a point-to-point or point-to-multipoint communications building block enabling transfer of data over a variety of high-speed serial links including smpte 292m and smpte 259m video applications. it supports signaling rates in the range of 195 to 1500 mbps per serial link. the transmit and receive channels are independent and can operate simultaneously at different rates. the transmit channel accepts 10-bit parallel characters in an input register and converts them to serial data. the receive channel accepts serial data and converts it to 10-bit parallel characters and presents t hese characters to an output register. the received serial data can also be reclocked and retransmitted through the reclocker serial outputs. figure 1 illustrates typical connections between independent video co- processors and corresponding CYV15G0104TRB chips. the CYV15G0104TRB satisfies the smpte 259m and smpte 292m compliance as per smpte eg34-1999 patho- logical test requirements. as a second-generation hotlink device, the CYV15G0104TRB extends the hotlink family with enhanced levels of integration and faster data rates, while maintaining serial-link compatibility (data and bist) with other hotlink devices. the transmit (tx) channel of the CYV15G0104TRB hotlink ii device accepts scrambled 10-bit transmission characters. these characters are serialized and output from dual positive ecl (pecl) compatible differential trans- mission-line drivers at a bit-rate of either 10- or 20-times the input reference clock for that channel. the receive (rx) channel of the CYV15G0104TRB hotlink ii device accepts a serial bit-stream from one of two selectable pecl-compatible differential line receivers, and using a completely integrated clock and data recovery pll, recovers the timing information necessary for data reconstruction. the recovered bit-stream is reclocked and retransmitted through the reclocker serial outputs. also, the recovered serial data is deserialized and presented to the destination host system. the transmit and receive channels contain an independent bist pattern generator and checker, respectively. this bist hardware allows at-speed testin g of the high-speed serial data paths in each transmit and re ceive section, and across the interconnecting links. figure 1. hotlink ii? system connections video coprocessor 10 10 video coprocessor 10 10 serial links independent CYV15G0104TRB independent device device channel CYV15G0104TRB channel reclocked output reclocked output
CYV15G0104TRB document #: 38-02100 rev. *b page 2 of 27 the CYV15G0104TRB is ideal for smpte applications where different data rates and serial interface standards are necessary for each channel. some applications include multi- format routers, switchers, fo rmat converters, sdi monitors, cameras, and camera control units. CYV15G0104TRB serializer and reclocking deserializer logic block diagram x10 serializer tx x10 deserializer reclocker rx txdb[9:0] rxda[9:0] toutb1 toutb2 routa1 routa2 ina1 ina2 phase align buffer refclkb trgclka
CYV15G0104TRB document #: 38-02100 rev. *b page 3 of 27 ina1+ ina1? ina2+ ina2? insela clock & data recovery pll shifter lfia 10 rxda[9:0] receive signal monitor output register rxclka+ rxclka? 2 jtag boundary scan controller tdo tms tclk tdi reset reclocking deserializer path block diagram trst rxpllpda spdsela ulca rxratea 10 bist lfsr 10 rxbista[1:0] ldtden sdasel[2..1]a[1:0] routa1+ routa1? routa2+ routa2? roe[2..1]a bit-rate clock character-rate clock reclocker reclkoa register recovered character clock recovered serial data trgclka x2 trgratea repdoa biststa clock multiplier output pll roe[2..1]a shifter serializer path block diagram txrateb input register phase-align buffer spdselb refclkb+ refclkb? transmit pll clock multiplier txclkb bit-rate clock character-rate clock toutb1+ toutb1? toutb2+ toutb2? phase-align buffer transmit pll clock multiplier toe[2..1]b txckselb = internal signal txerrb txclkob txdb[9:0] 10 10 pabrstb toe[2..1]b 1 0 bist lfsr 10 txbistb 10 wren addr[2:0] data[6:0] device configuration and control block diagram = internal signal rxratea rxpllpda txrateb txckselb toe[2..1]b pabrstb device configuration and control interface sdasel[2..1]a[1:0] rxbista[1:0] txbistb roe[2..1]a trgratea
CYV15G0104TRB document #: 38-02100 rev. *b page 4 of 27 pin configuration (top view) [1] note: 1. nc = do not connect. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a nc nc nc nc v cc nc tout b1? gnd gnd tout b2? in a1? rout a1? gnd in a2? rout a2? v cc v cc nc v cc nc b v cc nc v cc nc v cc v cc tout b1+ gnd nc tout b2+ in a1+ rout a1+ gnd in a2+ rout a2+ v cc nc nc nc nc c tdi tms v cc v cc v cc nc nc gnd data [6] data [4] data [2] data [0] gnd nc spd selb v cc ldtd en trst gnd tdo d tclk reset v cc insela v cc ulca nc gnd data [5] data [3] data [1] gnd gnd gnd nc v cc nc v cc scan en2 tmen3 e v cc v cc v cc v cc v cc v cc v cc v cc f nc nc v cc nc v cc nc nc nc g gnd wren gnd gnd nc nc spd sela nc h gnd gnd gnd gnd gnd gnd gnd gnd j gnd gnd gnd gnd nc nc nc nc k nc nc gnd gnd nc nc nc nc l nc nc nc gnd nc nc nc gnd m nc nc nc nc nc nc nc gnd n gnd gnd gnd gnd gnd gnd gnd gnd p nc nc nc nc gnd gnd gnd gnd r nc nc nc nc v cc v cc v cc v cc t v cc v cc v cc v cc v cc v cc v cc v cc u tx db[0] tx db[1] tx db[2] tx db[9] v cc nc nc gnd gnd addr [0] ref clkb? gnd gnd gnd v cc v cc rx da[4] v cc bist sta rx da[0] v tx db[3] tx db[4] tx db[8] nc v cc nc nc gnd nc gnd ref clkb+ re clkoa gnd gnd v cc v cc rx da[9] rx da[5] rx da[2] rx da[1] w tx db[5] tx db[7] nc nc v cc nc nc gnd addr [2] addr [1] rx clka+ repdo a gnd gnd v cc v cc lfi a trg clka+ rx da[6] rx da[3] y tx db[6] tx clkb nc nc v cc nc nc gnd tx clkob nc gnd rx clka? gnd gnd v cc v cc tx errb trg clka? rx da[8] rx da[7]
CYV15G0104TRB document #: 38-02100 rev. *b page 5 of 27 pin configuration (bottom view) [1] 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a nc v cc nc v cc v cc rout a2? in a2? gnd rout a1? in a1? tout b2? gnd gnd tout b1? nc v cc nc nc nc nc b nc nc nc nc v cc rout a2+ in a2+ gnd rout a1+ in a1+ tout b2+ nc gnd tout b1+ v cc v cc nc v cc nc v cc c tdo gnd trst ldtd en v cc spd selb nc gnd data [0] data [2] data [4] data [6] gnd nc nc v cc v cc v cc tms tdi d tmen3 scan en2 v cc nc v cc nc gnd gnd gnd data [1] data [3] data [5] gnd nc ulca v cc insela v cc reset tclk e v cc v cc v cc v cc v cc v cc v cc v cc f nc nc nc v cc nc v cc nc nc g nc spd sela nc nc gnd gnd wren gnd h gnd gnd gnd gnd gnd gnd gnd gnd j nc nc nc nc gnd gnd gnd gnd k nc nc nc nc gnd gnd nc nc l gndncncnc gnd nc nc nc m gndncncnc nc nc nc nc n gnd gnd gnd gnd gnd gnd gnd gnd p gnd gnd gnd gnd nc nc nc nc r v cc v cc v cc v cc nc nc nc nc t v cc v cc v cc v cc v cc v cc v cc v cc u rx da[0] bist sta v cc rx da[4] v cc v cc gnd gnd gnd ref clkb? addr [0] gnd gnd nc nc v cc tx db[9] tx db[2] tx db[1] tx db[0] v rx da[1] rx da[2] rx da[5] rx da[9] v cc v cc gnd gnd re clkoa ref clkb+ gnd nc gnd nc nc v cc nc tx db[8] tx db[4] tx db[3] w rx da[3] rx da[6] trg clka+ lfi a v cc v cc gnd gnd repdo a rx clka+ addr [1] addr [2] gnd nc nc v cc nc nc tx db[7] tx db[5] y rx da[7] rx da[8] trg clka? tx errb v cc v cc gnd gnd rx clka? gnd nc tx clkob gnd nc nc v cc nc nc tx clkb tx db[6]
CYV15G0104TRB document #: 38-02100 rev. *b page 6 of 27 pin definitions CYV15G0104TRB hotlink ii serializer and reclocking deserializer name i/o characteristics signal description transmit path data and status signals txdb[9:0] lvttl input, synchronous, sampled by txclkb or refclkb [2] transmit data inputs . txdb[9:0] data inputs are capt ured on the rising edge of the transmit interface clock. the transmit interf ace clock is selected by the txckselb latch via the device configuration interface. txerrb lvttl output, synchronous to refclkb [3] , asynchronous to transmit channel enable / disable, asynchronous to loss or return of refclkb transmit path error . txerrb is asserted high to indicate detection of a transmit phase-align buffer underflow or overflow. if an underflow or overflow condition is detected, txerrb, is asserted high and rema ins asserted until the transmit phase-align buffer is re-centered with the pabrstb latc h via the device configur ation interface. when txbistb = 0, the bist progress is pres ented on the txerrb output. the txerrb signal pulses high for one transmit-character clock period to indicate a pass through the bist sequence once every 511 character times. txerrb is also asserted high, when any of the following conditions is true: ? the txpll is powered down. this occurs when toe2b and toe1b are both disabled by setting toe2b = 0 and toe1b = 0. ? the absence of the refclkb signal. transmit path clock signals refclkb differential lvpecl or single-ended lvttl input clock reference clock . refclkb clock inputs are used as the timing reference for the transmit pll. this input clock may also be se lected to clock the transmit parallel interface. when driven by a single-ended lvcmos or lvttl clock source, connect the clock source to either the true or complement refclkb input, and leave the alternate refclkb input open (floating). when dr iven by an lvpecl clock source, th e clock must be a differential clock, using both inputs. txclkb lvttl clock input, internal pull-down transmit path input clock . when configuration latch tx ckselb = 0, the associated txclkb input is selected as the character-rate input clock for the txdb[9:0] input. in this mode, the txclkb input must be frequency- coherent to its txclkob output clock, but may be offset in phase by any amount. once initialized, txclkb is allowed to drift in phase by as much as 180 degrees. if t he input phase of txclkb drifts beyond the handling capacity of the phase align buffer, txerrb is asserted to indicate the loss of data, and remains asserted until the phase align buffer is initialized. the phase of txclkb relative to refclkb is initialized when the configuration latch pabrstb is written as 0. when txerrb is deasserted, th e phase align buffer is initialized and input characters are correctly captured. txclkob lvttl output transmit clock output . txclkob output clock is synthesized by the transmit pll and operates synchronous to the internal tr ansmit character clock. txclkob operates at either the same frequency as refclkb (t xrateb = 0), or at twice the frequency of refclkb (txrateb = 1). the transmit clock outputs have no fixed phase relationship to refclkb. receive path data and status signals rxda[9:0] lvttl output, synchronous to the rxclka output parallel data output . rxda[9:0] parallel data outputs change relative to the receive interface clock. if rxclka is a full-rate cl ock, the rxclka clock outputs are comple- mentary clocks operating at the character rate. the rxda[9:0] outputs for the associated receive channels follow rising edge of rxclka+ or falling edge of rxclka?. if rxclka is a half-rate clock, the rxclka clock ou tputs are complementary clocks operating at half the character rate. the rxda[9:0] outputs for the associated receive channels follow both the falling and rising edges of the associated rxclka clock outputs. when bist is enabled on the receive channel , the bist status is presented on the rxda[1:0] and biststa outputs. see table 6 for each status reported by the bist state machine. also, while bist is enabled, the rxda[9:2] outputs should be ignored. notes: 2. when refclkb is configured for half-rate operation, these i nputs are sampled relative to both the rising and falling edges o f the associated refclkb. 3. when refclkb is configured for half-rate operation, this output is presented relative to both the rising and falling edges o f the associated refclkb.
CYV15G0104TRB document #: 38-02100 rev. *b page 7 of 27 biststa lvttl output, synchronous to the rxclka output bist status output. when rxbista[1:0] = 10, bi ststa (along with rxda[1:0]) displays the status of th e bist reception. see table 6 for the bist stat us reported for each combination of biststa and rxda[1:0]. when rxbista[1:0] 10, biststa should be ignored. repdoa asynchronous to reclocker output channel enable/disable reclocker powered down status output. repdoa is asserted high, when the reclocker output logic is powered down. this occurs when roe2a and roe1a are both disabled by setting roe2a = 0 and roe1a = 0. receive path clock signals trgclka differential lvpecl or single-ended lvttl input clock cdr pll training clock . trgclka clock inputs are used as the reference source for the frequency detector (range controller) of the receive pll to reduce pll acquisition time. in the presence of valid serial data, the recovered clock output of the receive cdr pll (rxclka) has no frequency or phase relationship with trgclka. when driven by a single-ended lvcmos or lvttl clock source, connect the clock source to either the true or complement trgclka input, and leave the alternate trgclka input open (floating). when dr iven by an lvpecl clock source, th e clock must be a differential clock, using both inputs. rxclka lvttl output clock receive clock output . rxclka is the receive interface clock used to control timing of the rxda[9:0] parallel outputs. these true and complement clocks are used to control timing of data output transf ers. these clocks are output cont inuously at either the half- character rate (1/20 th the serial bit-rate) or character rate (1/10 th the serial bit-rate) of the data being received, as selected by rxratea. reclkoa lvttl output reclocker clock output . reclkoa output clock is synthes ized by the reclocker output pll and operates synchronous to the inter nal recovered character clock. reclkoa operates at either the same frequency as rxclka (rxratea = 0), or at twice the frequency of rxclka (rxratea = 1).the reclocker clock outputs have no fixed phase relationship to rxclka. device control signals reset lvttl input, asynchronous, internal pull-up asynchronous device reset . reset initializes all state machines, counters, and configuration latches in the device to a known state. reset must be asserted low for a minimum pulse width. when the reset is removed, all state machines, counters and config- uration latches are at an initial state. see ta ble 4 for the initialize values of the device configuration latches. ldtden lvttl input, internal pull-up level detect transition density enable . when ldtden is high, the signal level detector, range controller, and transition de nsity detector are all enabled to determine if the rxpll tracks trgclka or the selected input serial data stream. if the signal level detector, range controller, or transition densit y detector are out of their respective limits while ldtden is high, the rxpll locks to trgclka until such a time they become valid. sdasel[2..1]a[1:0] is used to configure the trip level of the signal level detector. the transition density detector limit is one transition in every 60 consecutive bits. when ldtden is low, only the range controller is used to determine if the rxpll tracks trgclka or the selected input serial dat a stream. it is recommended to set ldtden = high. ulca lvttl input, internal pull-up use local clock . when ulca is low, the rxpll is forced to lock to trgclka instead of the received serial data stream. while ulca is low, the link fault indicator lfia is low indicating a link fault. when ulca is high, the rxpll performs clock and data recovery functions on the input data streams. this function is used in applications in which a stable rxclka is needed. in cases when there is an absence of valid data transitions for a long period of time, or the high-gain differential serial input s (ina) are left floating, there may be brief frequency excursions of the rxclka outputs from trgclka. pin definitions (continued) CYV15G0104TRB hotlink ii serializer and reclocking deserializer name i/o characteristics signal description
CYV15G0104TRB document #: 38-02100 rev. *b page 8 of 27 spdsela spdselb 3-level select [4] static control input serial rate select . the spdsela and spdselb inputs specify the operating signaling- rate range of the receive and transmit pll, respectively. low = 195 ? 400 mbd mid = 400 ? 800 mbd high = 800 ? 1500 mbd. insela lvttl input, asynchronous receive input selector . the insela input determines which external serial bit stream is passed to the receiver?s clock and data recovery circuit. when insela is high, the primary differential serial data input, ina1, is selected for the receive channel. when insela is low, the secondary differential serial data input, ina2, is selected for the receive channel. lfia lvttl output, asynchronous link fault indication output . lfia is an output status indicator signal. lfia is the logical or of six internal conditions. lfia is asserted low when any of the following conditions is true: ? received serial data rate outside expected range ? analog amplitude below expected levels ? transition density lower than expected ? receive channel disabled ?ulca is low ? absence of trgclka. device configuration and control bus signals wren lvttl input, asynchronous, internal pull-up control write enable . the wren input writes the values of the data[6:0] bus into the latch specified by the addres s location on the addr[2:0] bus. [5] addr[2:0] lvttl input asynchronous, internal pull-up control addressing bus . the addr[2:0] bus is the input address bus used to configure the device. the wren input writes the values of the data[6:0] bus into the latch specified by the address location on the addr[2:0] bus. [5] ta ble 4 lists the configuration latches within the device, and the init ialization value of the latches upon the assertion of reset . table 5 shows how the latches are mapped in the device. data[6:0] lvttl input asynchronous, internal pull-up control data bus . the data[6:0] bus is the input data bus used to configure the device. the wren input writes the values of the data[6:0 ] bus into the latch specified by address location on the addr[2:0] bus. [5 ] table 4 lists the configuration la tches within the device, and the initialization value of the latches upon the assertion of reset . table 5 shows how the latches are mapped in the device. internal device configuration latches rxratea internal latch [6] receive clock rate select . sdasel[2..1] a[1:0] internal latch [6] signal detect amplitude select . txckselb internal latch [6] transmit clock select . txrateb internal latch [6] transmit pll clock rate select . trgratea internal latch [6] reclocker output pll clock rate select . rxpllpda internal latch [6] receive channel power control . rxbista[1:0] internal latch [6] receive bist disabled . txbistb internal latch [6] transmit bist disabled . toe2b internal latch [6] transmitter differential serial output driver 2 enable . toe1b internal latch [6] transmitter differential serial output driver 1 enable . notes: 4. 3-level select inputs are used for static configuration. these are ternary inputs that make use of logic levels of low, mid, and high. the low level is usually implemented by direct connection to v ss (ground). the high level is usually implemented by direct connection to v cc (power). the mid level is usually implemented by not connecting the input (left floating), which allows it to self bias to the proper level. 5. see device configuration and control interface for detailed information on the operation of the configuration interface. 6. see device configuration and control interface for detailed information on the internal latches. pin definitions (continued) CYV15G0104TRB hotlink ii serializer and reclocking deserializer name i/o characteristics signal description
CYV15G0104TRB document #: 38-02100 rev. *b page 9 of 27 CYV15G0104TRB hotlink ii operation the CYV15G0104TRB is a highly configurable, independent clocking device designed to support reliable transfer of large quantities of digital video data, using high-speed serial links from multiple sources to multiple destinations. CYV15G0104TRB transmit data path input register the parallel input bus txdb[9:0] can be clocked in using txclkb (txckselb = 0) or refclkb (txckselb = 1). roe2a internal latch [6] reclocker differential serial output driver 2 enable . roe1a internal latch [6] reclocker differential serial output driver 1 enable . pabrstb internal latch [6] transmit clock phase alignment buffer reset . factory test modes scanen2 lvttl input, internal pull-down factory test 2. scanen2 input is for factory testing only. this input may be left as a no connect, or gnd only. tmen3 lvttl input, internal pull-down factory test 3 . tmen3 input is for factory testing only. this input may be left as a no connect, or gnd only. analog i/o toutb1 cml differential output transmitter primary differe ntial serial data output . the transmitter toutb1 pecl- compatible cml outputs (+3.3v referenced) are capable of driving terminated trans- mission lines or standard fiber-optic tran smitter modules, and must be ac-coupled for pecl-compatible connections. toutb2 cml differential output transmitter secondary differential serial data output . the transmitter toutb2 pecl- compatible cml outputs (+3.3v referenced) ar e capable of driving terminated transmission lines or standard fiber-optic transmi tter modules, and must be ac-coupled for pecl-compatible connections. routa1 cml differential output reclocker primary differential serial data output . the reclocker routa1 pecl- compatible cml outputs (+3.3v referenced) are capable of driving terminated trans- mission lines or standard fiber-optic tran smitter modules, and must be ac-coupled for pecl-compatible connections. routa2 cml differential output reclocker secondary differential serial data output . the reclocker routa2 pecl- compatible cml outputs (+3.3v referenced) ar e capable of driving terminated transmission lines or standard fiber-optic transmi tter modules, and must be ac-coupled for pecl-compatible connections. ina1 differential input primary differential serial data input . the ina1 input accepts the serial data stream for deserialization. the ina1 serial stream is passed to the receive cdr circuit to extract the data content when insela = high. ina2 differential input secondary differential serial data input . the ina2 input accepts the serial data stream for deserialization. the ina2 serial st ream is passed to the receiver cdr circuit to extract the data content when insela = low. jtag interface tms lvttl input, internal pull-up test mode select . used to control access to the jtag test modes. if maintained high for 5 tclk cycles, the jtag test controller is reset. tclk lvttl input, internal pull-down jtag test clock . tdo 3-state lvttl output test data out . jtag data output buffer. high-z while jtag test mode is not selected. tdi lvttl input, internal pull-up test data in . jtag data input port. trst lvttl input, internal pull-up jtag reset signal . when asserted (low), this inpu t asynchronously resets the jtag test access port controller. power v cc +3.3v power . gnd signal and power ground for all internal circuits . pin definitions (continued) CYV15G0104TRB hotlink ii serializer and reclocking deserializer name i/o characteristics signal description
CYV15G0104TRB document #: 38-02100 rev. *b page 10 of 27 phase-align buffer data from the input register is passed to the phase-align buffer, when the txdb[9:0] input register is clocked using txclkba (txckselb = 0) or when refclkb is a half-rate clock (txckselb = 1 and txrateb = 1). when the txdb[9:0] input register is clocked using refclkb (txcksela = 1) and refclkb is a full-rate clock (txrateb = 0), the associated phase alignment buffer in the transmit path is bypassed. these buffers are used to absorb clock phase differences between the txclkb input clock and the internal character clock for that channel. once initialized, txclkb is allowed to drift in phase as much as 180 degrees. if the input phase of txclkb drifts beyond the handling capacity of the phase align buffer, txerrb is asserted to indicate the loss of data, and remains asserted until the phase align buffer is initialized. the phase of txclkb relative to its internal ch aracter rate clock is initialized when the configuration latch p abrstb is written as 0. when the associated txerrb is deasserted, the phase align buffer is initialized and input characters are correctly captured. if the phase offset, between the initialized location of the input clock and refclkb, exceeds the skew handling capabilities of the phase-align buffer, an error is reported on that channel?s txerrb output. this output indicates an error continuously until the phase-align buffer for that channel is reset. while the error remains active, the transmitter for that channel outputs a continuous ?1001111000? character to indicate to the remote receiver that an error condition is present in the link. transmit bist the transmit channel contains an internal pattern generator that can be used to validate both the link and device operation. this generator is enabled by th e txbistb latch via the device configuration interface. when enabled, a register in the transmit channel becomes a si gnature pattern generator by logically converting to a linear feedback shift register (lfsr). this lfsr generates a 511-character sequence. this provides a predictable yet pseudo-random sequence that can be matched to an identical lfsr in the attached receiver(s). a device reset (reset sampled low) presets the bist enable latches to disable bist on all channels. all data present at the txdb[9:0] inputs are ignored when bist is active on that channel. transmit pll clock multiplier the transmit pll clock multip lier accepts a character-rate or half-character-rate external cl ock at the refclkb input, and that clock is multiplied by 10 or 20 (as selected by txrateb) to generate a bit-rate clock for use by the transmit shifter. it also provides a character-rate clock used by the transmit paths, and outputs this character rate clock as txclkob. the clock multiplier pll can accept a refclkb input between 19.5 mhz and 150 mhz, however, this clock range is limited by the operating mode of the CYV15G0104TRB clock multiplier (txrateb) and by t he level on the spdselb input. spdselb is a 3-level select [4] input that selects one of three operating ranges for the serial data outputs of the transmit channel. the operating serial signaling-rate and allowable range of refclkb frequencies are listed in table 1 . the refclkb inputs are differential inputs with each input internally biased to 1.4v. if the refclkb+ input is connected to a ttl, lvttl, or lvcmos clock source, the input signal is recognized when it passes through the internally biased reference point. when driven by a single-ended ttl, lvttl, or lvcmos clock source, connect the clock source to either the true or complement refclkb input, and leave the alternate refclkb input open (floating). when both the refclkb+ and refclkb? inputs are connected, the clock source must be a differential clock. this can either be a differential lvpecl clock that is dc-or ac-coupled or a differential lvttl or lvcmos clock. by connecting the refclkb? input to an external voltage source, it is possible to adjust the reference point of the refclkb+ input for alternate logic levels. when doing so, it is necessary to ensure that the input differential crossing point remains within the parametric range supported by the input. transmit serial output drivers the serial output interface dr ivers use differential current mode logic (cml) drivers to provide source-matched drivers for 50 ? transmission lines. these drivers accept data from the transmit shifter. these drivers have signal swings equivalent to that of standard pecl drivers, and are capable of driving ac-coupled optical modules or transmission lines. transmit channels enabled each driver can be enabled or disabled separately via the device configuration interface. when a driver is disabled via t he configuration interface, it is internally powered down to reduce device power. if both transmit serial drivers are in th is disabled state, the transmitter internal logic for that channel is also powered down. a device reset (reset sampled low) disables all output drivers. note . when the disabled transmit channel (i.e., both outputs disabled) is re-enabled: ? the data on the transmit se rial outputs may not meet all timing specifications for up to 250 s ? the state of the phase-align buffer cannot be guaranteed, and a phase-align reset is required if the phase-align buffer is used CYV15G0104TRB receive data path serial line receivers two differential line receivers, ina1 and ina2, are available on the receive channel for accepting serial data streams. the active serial line receiver is selected using the table 1. operating speed settings spdselb txrateb refclkb frequency (mhz) signaling rate (mbps) low 1 reserved 195?400 0 19.5?40 mid (open) 1 20?40 400?800 0 40?80 high 1 40?75 800?1500 0 80?150
CYV15G0104TRB document #: 38-02100 rev. *b page 11 of 27 insela input. the serial line receiver inputs are differential, and can accommodate wire interconnect and filtering losses or transmission line attenuation greater than 16 db. for normal operation, these inputs should receive a signal of at least vi diff > 100 mv, or 200 mv peak-to-peak differential. each line receiver can be dc- or ac-coupled to +3.3v powered fiber-optic interface modules (any ecl/pecl family, not limited to 100k pecl) or ac-coupled to +5v powered optical modules. the common-mode tolerance of these line receivers accommodates a wide range of signal termination voltages. each receiver provides internal dc-restoration, to the center of the receiver?s common mode range, for ac- coupled signals. signal detect/link fault each selected line receiver (i.e., that routed to the clock and data recovery pll) is simultaneously monitored for ? analog amplitude above amplitude level selected by sdasela ? transition density above the specified limit ? range controls report the received data stream inside normal frequency range (1500 ppm [24] ) ? receive channel enabled ? presence of reference clock ?ulca is not asserted. all of these conditions must be valid for the signal detect block to indicate a valid signal is present. this status is presented on the lfia (link fault indicator) output associated with each receive channel, which changes synchronous to the receive interface clock. analog amplitude while most signal monitors are based on fixed constants, the analog amplitude level detection is adjustable to allow operation with highly attenuated signals, or in high-noise environments. the analog amplitude level detection is set by the sdasela latch via device configuration interface. the sdasela latch sets the trip point for the detection of a valid signal at one of three levels, as listed in table 2 . this control input affects the analog monitors for all receive channels. the analog signal detect monitors are active for the line receiver as selected by the insela input. transition density the transition dete ction logic checks for the absence of transitions spanning greater than six transmission characters (60 bits). if no transitions are present in the data received, the detection logic for that channel asserts lfia . range controls the cdr circuit includes logic to monitor the frequency of the pll voltage controlled oscillator (vco) used to sample the incoming data stream. this logic ensures that the vco operates at, or near the rate of the incoming data stream for two primary cases: ? when the incoming data stream resumes after a time in which it has been ?missing.? ? when the incoming data stream is outside the acceptable signaling rate range. to perform this function, the frequency of the rxpll vco is periodically compared to the frequency of the trgclka input. if the vco is running at a frequency beyond 1500ppm [24] as defined by the trgclka frequency, it is periodically forced to the correct frequency (as defined by trgclka, spdsela, and trgr atea) and then released in an attempt to lock to the input data stream. the sampling and relock period of the range control is calcu- lated as follows: range_control_ sampling_period = (recovered byte cloc k period) * (4096). during the time that the range control forces the rxpll vco to track trgclka, the lfia output is asserted low. after a valid serial data stream is applied, it may take up to one range control sampling period before the pll locks to the input data st ream, after which lfia should be high. the operating serial signaling-rate and allowable range of trgclka frequencies are listed in table 3 . receive channel enabled the receive channel can be enabled or disabled through the rxpllpda input latch as cont rolled by the device configu- ration interface. when rxpllpda = 0, the cdr pll and analog circuitry of the channel are disabled. any disabled channel indicates a constant link fault condition on the lfia output. when rxpllpda = 1, the cdr pll and receive channel are enabled to receive a serial stream. note . when the disabled receive channel is reenabled, the status of the lfia output and data on the parallel outputs for the associated channel may be indeterminate for up to 2 ms. clock/data recovery the extraction of a bit-rate clock and recovery of bits from the received serial stream is performed by a separate cdr block within the receive channel. the clock extraction function is table 2. analog amplitude detect valid signal levels [7] sdasela typical signal with peak amplitudes above 00 analog signal detector is disabled 01 140 mv p-p differential 10 280 mv p-p differential 11 420 mv p-p differential note: 7. the peak amplitudes listed in this table are for typical wavefo rms that have generally 3?4 transitions for every ten bits. in a worse case environment the signals may have a sine-wave appearance (highest transition density with repeating 0101...). signal peak amplitudes levels within this environment type could increase the values in the table above by approximately 100 mv. table 3. operating speed settings spdsela trgratea trgclka frequency (mhz) signaling rate (mbps) low 1 reserved 195?400 0 19.5?40 mid (open) 1 20?40 400?800 0 40?80 high 1 40?75 800?1500 0 80?150
CYV15G0104TRB document #: 38-02100 rev. *b page 12 of 27 performed by an integrated pll that tracks the frequency of the transitions in the incoming bit stream and aligns the phase of the internal bit-rate clock to the transitions in the selected serial data stream. each cdr accepts a character-rate (bit-rate 10) or half- character-rate (bit-rate 20) training clock from the trgclka input. this tr gclka input is used to ? ensure that the vco (within the cdr) is operating at the correct frequency (rather than a harmonic of the bit-rate) ? reduce pll acquisition time ? limit unlocked frequency excursions of the cdr vco when there is no input data present at the selected serial line receiver. regardless of the type of signa l present, the cdr attempts to recover a data stream from i t. if the signaling rate of the recovered data stream is outside the limits set by the range control monitors, the cdr tracks trgclka instead of the data stream. once the cdr output (rxclka) frequency returns back close to the trgclka frequency, the cdr input is switched back to the input data stream. if no data is present at the selected line receiver, this switching behavior may result in brief rxclka frequency excursions from trgclka. however, the validity of the input data stream is indicated by the lfia output. the frequency of trgclka is required to be within 1500ppm [24] of the frequency of the clock that drives the refclkb input of the remote trans- mitter to ensure a lock to the incoming data stream. this large ppm tolerance allows the cdr pll to reliably receive a 1.485 or 1.485/1.001 gbps smpte hd-sdi data stream with a constant trgclk frequency. for systems using multiple or redundant connections, the lfia output can be used to select an alternate data stream. when an lfia indication is detected, external logic can toggle selection of the ina1 and ina2 input through the insela input. when a port switch takes place, it is necessary for the receive pll for that channel to reacquire the new serial stream. reclocker the receive channel performs a reclocker function on the incoming serial data. to do this, the clock and data recovery pll first recovers the clock from the data. the data is retimed by the recovered clock and then passed to an output register. also, the recovered character clock from the receive pll is passed to the reclocker output pll which generates the bit clock that is used to clock the retimed data into the output register. this data stream is then transmitted through the differential serial outputs. reclocker serial output drivers the serial output interface dr ivers use differential current mode logic (cml) drivers to provide source-matched drivers for 50 ? transmission lines. these drivers accept data from the reclocker output register in the reclocker channel. these drivers have signal swings equivalent to that of standard pecl drivers, and are capable of driving ac-coupled optical modules or transmission lines. reclocker output channels enabled each driver can be enabled or disabled separately via the device configuration interface. when a driver is disabled via t he configuration interface, it is internally powered down to reduce device power. if both reclocker serial drivers are in this disabled state, the internal reclocker logic is also powered down. the deserialization logic and parallel outputs will remain enabled. a device reset (reset sampled low) disables all output drivers. note . when the disabled reclocker function (i.e., both outputs disabled) is re-enabled, the data on the reclocker serial outputs may not meet all timing specifications for up to 250 s. output bus the receive channel presents a 10-bit data signal (and a bist status signal when rxbista[1:0] = 10). receive bist operation the receiver channel contains an internal pattern checker that can be used to validate both device and link operation. these pattern checkers are enabled by the rxbista[1:0] latch via the device configuration interfac e. when enabled, a register in the receive channel becomes a signature pattern generator and checker by logically converting to a linear feedback shift register (lfsr). this lfsr generates a 511-character sequence. this provides a predictable yet pseudo-random sequence that can be matched to an identical lfsr in the attached transmitter(s). when synchronized with the received data stream, the receiver checks each character from the deserializer with each character generated by the lfsr and indicates compare errors and bist status at the rxda[1:0] and biststa bits of the output register. the bist status bus {biststa, rxda[0], rxda[1]} indicates 010b or 100b for one character period per bist loop to indicate loop completion. this status can be used to check test pattern progress. the specific status reported by the bist state ma chine is listed in table 6 . these same codes are reported on the receive status outputs. if the number of invalid characters received ever exceeds the number of valid characters by 16, the receive bist state machine aborts the compare operations and resets the lfsr to look for the start of the bist sequence again. a device reset (reset sampled low) presets the bist enable latches to disable bist on all channels. bist status state machine when a receive path is enabled to look for and compare the received data stream with t he bist pattern, the {biststa, rxda[1:0]} bits identify the pr esent state of the bist compare operation. the bist state machine has multiple states, as shown in figure 2 and table 6 . when the receive pll detects an out-of- lock condition, the bist state is forced to the start-of-bist state, regardless of the pres ent state of the bist state machine. if the number of detected errors ever exceeds the number of valid matches by great er than 16, the state machine is forced to the wait_for_bist state where it monitors the receive path for the first character of the next bist sequence. power control the CYV15G0104TRB supports user control of the powered up or down state of each transmit and receive channel. the receive channels are controlled by the rxpllpda latch via
CYV15G0104TRB document #: 38-02100 rev. *b page 13 of 27 the device configuration interf ace. when rxpllpda = 0, the receive pll and analog circuitry of the channel is disabled. the transmit channel is controlled by the toe1b and the toe2b latches via the device co nfiguration interface. the reclocker function is controlled by the roe1a and the roe2a latches via the device configuration interface. when a driver is disabled via the configuration interface, it is internally powered down to reduce device power. if both serial drivers for a channel are in this disabled state, the associated internal logic for that channel is also powered down. when the reclocker serial drivers are disabled, the reclocker function will be disabled, but the deserialization logic and parallel outputs will remain enabled. device reset state when the cyv15g0104 trb is reset by assertion of reset , all state machines, counters, and configuration latches in the device are initialized to a reset state. see table 4 for the initialize values of the configuration latches. following a device reset, it is necessary to enable the transmit and receive channels used for normal operation. this can be done by sequencing the appropriate values on the device configuration interface. [5] device configuration and control interface the CYV15G0104TRB is highly configurable via the configu- ration interface. the configurat ion interface allows the trans- mitter and reclocker to be configured independently. ta ble 4 lists the configuration latches within the device including the initialization value of the latches upon the assertion of reset . table 5 shows how the latches are mapped in the device. each row in the table 5 maps to a 7-bit latch bank. there are 6 such write-only latch banks. when wren = 0, the logic value in the data[6:0] is latched to the latch bank specified by the values in addr[2:0]. the second column of table 5 specifies the channels associated with the corresponding latch bank. for example, the first three latch banks (0,1 and 2) consist of configuration bits for the reclocker channel a. latch types there are two types of latch banks: static (s) and dynamic (d). each channel is configured by 2 static and 1 dynamic latch banks. the s type contain those settings that normally do not change for a given application, whereas the d type controls the settings that could change during the applicat ion's lifetime. the first and second rows of each channel (address numbers 0, 1, 5, and 6) are the static control latches. the third row of latches for each channel (address numbers 2 and 7) are the dynamic control latches that are associated with enabling dynamic functions within the device. address numbers 3 and 4 are internal test registers. static latch values there are some latches in the table that have a static value (i.e. 1, 0, or x). the latches that have a ?1? or ?0? must be configured with their corresponding value each time that their associated latch bank is confi gured. the latches that have an ?x? are don?t cares and can be configured with any value. table 4. device configuration and control latch descriptions name signal description rxratea receive clock rate select . the initialization value of the rxratea latch = 1. rxratea is used to select the rate of the rxclka clock output. when rxratea = 1, the rxclka clock outputs are complementary clocks that follow the recovered clock operating at half the character rate. data for the asso ciated receive channels should be latched alternately on the rising edge of rxclka+ and rxclka?. when rxratea = 0, the rxclka clock outputs are complementary clocks that follow the recovered clock operating at the character rate. data for the associ ated receive channels should be latched on the rising edge of rxclka+ or falling edge of rxclka?. sdasel1a[1:0] primary serial data input signal detector amplitude select . the initialization value of the sdasel1a[1:0] latch = 10. sdasel1a[1:0] sele cts the trip point for the detection of a valid signal for the ina1 primary differential seri al data inputs. when sdasel1a[1:0] = 00, the analog signal detector is disabled. when sdasel1a[1:0] = 01, the typical p-p differential voltage threshold level is 140 mv. when sdasel1a[1:0] = 10, the typical p-p differential voltage threshold level is 280 mv. when sdasel1a[1:0] = 11, the typical p-p differential voltage threshold level is 420 mv. sdasel2a[1:0] secondary serial data input si gnal detector amplitude select . the initialization value of the sdasel2a[1:0] latch = 10. sdase l2a[1:0] selects the trip point for the de tection of a vali d signal for the ina2 secondary differential serial data inputs. when sdasel2a[1:0] = 00, the analog signal detector is disabled when sdasel2a[1:0] = 01, the typical p-p differential voltage threshold level is 140 mv. when sdasel2a[1:0] = 10, the typical p-p differential voltage threshold level is 280 mv. when sdasel2a[1:0] = 11, the typical p-p differential voltage threshold level is 420 mv. trgratea training clock rate select . the initialization value of the trgratea latch = 0. trgratea is used to select the clock multiplier for the training clock input to the cdr pll. when trgratea = 0, the trgclka input is not multiplied before it is passed to the cdr pll. when trgratea = 1, the trgclka input is multiplied by 2 before it is passed to the cdr pll. trgratea = 1 and spdsela = low is an invalid state and this combination is reserved.
CYV15G0104TRB document #: 38-02100 rev. *b page 14 of 27 rxpllpda receive channel enable . the initialization value of the rxpllpda latch = 0. rxpllpda selects if the receive channel is enabled or powered-down. when r xpllpda = 0, the receive pll and analog circuitry are powered-down. when rxpllpda = 1, the re ceive pll and analog circuitry are enabled. rxbista[1:0] receive bist disable / smpte receive enable . the initialization value of the rxbista[1:0] latch = 11. for smpte data reception, rxbist a[1:0] should not remain in this initia lization state (11). rxbista[1:0] selects if receive bist is disabled or enabled and sets the device for smpte data reception. when rxbista[1:0] = 01, the receiver bist function is disabled and the device is set to rece ive smpte data. when rxbista[1:0] = 10, the receive bist function is e nabled and the device is set to receiv e bist data. rxbist a[1:0] = 00 and rxbista[1:0] = 11 are invalid states. roe2a reclocker secondary differential se rial data output driver enable . the initialization value of the roe2a latch = 0. roe2a selects if the routa2 secondary differ ential output drivers are enabled or disabled. when roe2a = 1, the associated serial data output driver is enabled allowing th e reclocked data to be transmitted. when roe2a = 0, the associated serial data output driver is disabled. when a driver is disabled via the configuration interface, it is internally powered down to reduce device power. if both serial drivers for a channel are in this disabled state, the reclocker logic is also powered down. a device reset (reset sampled low) disables all output drivers. roe1a reclocker primary differential seri al data output driver enable . the initialization value of the roe1a latch = 0. roe1a selects if the routa1 primary differ ential output drivers are ena bled or disabled. when roe1a = 1, the associated serial data output driver is enabled allowing th e reclocked data to be transmitted. when roe1a = 0, the associated serial data output driver is disabled. when a driver is disabled via the configuration interface, it is internally powered down to reduce device power. if both serial drivers for a channel are in this disabled state, the reclocker logic is also powered down. a device reset (reset sampled low) disables all output drivers. txckselb transmit clock select . the initialization value of the txckselb latch = 1. txckselb selects the clock source used to write data into the tr ansmit input register. when txckselb = 1, the input register txdb[9:0] is clocked by refclkb . in this mode, the phase alignment buffer in the transmit path is bypassed. when txckselb = 0, txclkb is used to clock in the input register txdb[9:0]. txrateb transmit pll clock rate select . the initialization value of the txrateb latch = 0. txrateb is used to select the clock multiplier for the transmit pll. when tx rateb = 0, the transmit p ll multiples the refclkb input by 10 to generate the serial bit-rate clock. w hen txrateb = 0, the txclkob output clocks are full-rate clocks and follow the frequency a nd duty cycle of the refclkb input. when txrateb = 1, the transmit pll multiplies the refclkb input by 20 to generate the serial bit-rate clock. when txrateb = 1, the txclkob output clocks are twice the frequency rate of the refclkb input. when txckselb = 1 and txrateb = 1, the transmit data inputs are captur ed using both the rising and falling edges of refclkb. txrateb = 1 and spdselb = low, is an invalid state and this combination is reserved. txbistb transmit bist disable . the initialization value of the txbistb latc h = 1. txbistb selects if the transmit bist is disabled or enabled. when txbistb = 1, the trans mit bist function is disabled. when txbistb = 0, the transmit bist function is enabled. toe2b secondary differential serial data output driver enable . the initialization value of the toe2b latch = 0. toe2b selects if the toutb2 secondary differential output drivers are enabled or disabled. when toe2b = 1, the associated serial data output driver is enabled a llowing data to be transmitted from the transmit shifter. when toe2b = 0, the associated serial data output driver is disabled. when a driver is disabled via the configuration interface, it is internally powered down to reduce device power. if both serial drivers for a channel are in this disabled state, the associated internal logi c for that channel is also powered down. a device reset (reset sampled low) disabl es all output drivers. toe1b primary differential serial data output driver enable . the initialization value of the toe1b latch = 0. toe1b selects if the toutb1 primary differential outp ut drivers are enabled or disabled. when toe1b = 1, the associated serial data output driver is enabled al lowing data to be transmitted from the transmit shifter. when toe1b = 0, the associated serial data output driver is disabled. when a driver is disabled via the configuration interface, it is internally powered down to reduce device power. if both serial drivers for a channel are in this disabled state, the associated internal logi c for that channel is also powered down. a device reset (reset sampled low) disabl es all output drivers. pabrstb transmit clock phase alignment buffer reset . the initialization value of the pabrstb latch = 1. the pabrstb is used to re-center the transmit phase al ign buffer. when the configuration latch pabrstb is written as a 0, the phase of the txclkb input clock rela tive to refclkb+/- is initialized. pabrstb is an asynchronous input, but is sampled by each txclkb to synchronize it to the internal clock domain. pabrstb is a self clearing latch. this eliminates the re quirement of writing a 1 to complete the initialization of the phase alignment buffer. table 4. device configuration and control latch descriptions (continued) name signal description
CYV15G0104TRB document #: 38-02100 rev. *b page 15 of 27 device configuration strategy the following is a series of ordered events needed to load the configuration latches on a per channel basis: 1. pulse reset low after device power-up. this operation resets both channels. 2. set the static latch banks for the target channel. 3. set the dynamic bank of latches for the target channel. enable the receive pll and/or transmit channel. if the receiver is enabled, set the device for smpte data reception (rxbista[1:0] = 01) or bist data reception (rxbista[1:0] = 10). 4. reset the phase alignment buffer. [optional if phase align buffer is bypassed.] jtag support the CYV15G0104TRB contains a jtag port to allow system level diagnosis of device interconnect. of the available jtag modes, boundary scan, and bypass are supported. this capability is present only on the lvttl inputs and outputs, the trgclka input, and the refclkb clock input. the high- speed serial inputs and outputs are not part of the jtag test chain. 3-level select inputs each 3-level select inputs reports as two bits in the scan register. these bits report t he low, mid, and high state of the associated input as 00, 10, and 11 respectively jtag id the jtag device id for the CYV15G0104TRB is ?0c811069?x. table 5. device control latch configuration table addr channel type data6 data5 data4 data3 data2 data1 data0 reset value 0 (000b) a s 1 0 x x 0 0 rxratea 1011111 1 (001b) a s sdasel2a[1] sdasel2a[0] sdasel1a[1] sdasel1a[0] x x trgratea 1010110 2 (010b) a d rxbista[1] rxpllpda rxbista[0] x roe2a roe1a x 1011001 3 (011b) internal test registers do not write to these addresses 4 (100b) 5 (101b) b s x x x x x 0 x 1011111 6 (110b) b s x x x x 0 txckselb txrateb 1010110 7 (111b) b d x 0 x txbistb toe2b toe1b pabrstb 1011001 table 6. receive bist status bits {biststa, rxda[0], rxda[1]} description receive bist status (receive bist = enabled) 000, 001 bist data compare . character compared correctly. 010 bist last good . last character of bist sequence detected and valid. 011 reserved. 100 bist last bad . last character of bist sequence detected invalid. 101 bist start . receive bist is enabled on this channel, but character compares have not yet commenced. this also indicates a pll out of lock condition. 110 bist error . while comparing characters, a mismatch was found in one or more of the character bits. 111 bist wait . the receiver is comparing characters but has not yet found the start of bist character to enable the lfsr.
CYV15G0104TRB document #: 38-02100 rev. *b page 16 of 27 receive bist detected low monitor data received {biststa, rxda[0], no rx pll out of lock yes, {biststa, rxda[0], rxda[1]} = bist_data_compare (000, 001) compare next character auto-abort condition mismatch end-of-bist state yes, {biststa, rxda[0], rxda[1]} = bist_last_bad (100) yes no no, {biststa, rxda[0], rxda[1]} = bist_error (110) match end-of-bist state yes, {biststa, rxda[0], rxda[1]} = bist_last_g ood (010) no {biststa, rxda[0], rxda[1]} = bist_data_compare (000, 001) figure 2. receive bist state machine start of bist detected {biststa, rxda[0], rxda[1]} = bist_wait (111) bist_start (101) rxda[1]} =
CYV15G0104TRB document #: 38-02100 rev. *b page 17 of 27 maximum ratings (above which the useful life may be impaired. user guidelines only, not tested.) storage temperature .............. .............. ...... ?65c to +150c ambient temperature with power applied........... .............. .............. ...... ?55c to +125c supply voltage to ground potential ............... ?0.5v to +3.8v dc voltage applied to lvttl outputs in high-z state .......................................?0.5v to v cc + 0.5v output current into lvttl outputs (low)..................60 ma dc input voltage....................................?0.5v to v cc + 0.5v static discharge voltage.......................................... > 2000 v (per mil-std-883, method 3015) latch-up current..................................................... > 200 ma power-up requirements the CYV15G0104TRB requires one power supply. the voltage on any input or i/o pin cannot exceed the power pin during power-up. operating range range ambient temperature v cc commercial 0c to +70c +3.3v 5% CYV15G0104TRB dc electrical characteristics parameter description test conditions min. max. unit lvttl-compatible outputs v oht output high voltage i oh = ? 4 ma, v cc = min. 2.4 v v olt output low voltage i ol = 4 ma, v cc = min. 0.4 v i ost output short circuit current v out = 0v [8] , v cc = 3.3v ?20 ?100 ma i ozl high-z output leakage current v out = 0v, v cc ?20 20 a lvttl-compatible inputs v iht input high voltage 2.0 v cc + 0.3 v v ilt input low voltage ?0.5 0.8 v i iht input high current refclkb input, v in = v cc 1.5 ma other inputs, v in = v cc +40 a i ilt input low current refclkb input, v in = 0.0v ?1.5 ma other inputs, v in = 0.0v ?40 a i ihpdt input high current with internal pull-down v in = v cc +200 a i ilput input low current with internal pull-up v in = 0.0v ?200 a lvdiff inputs: refclkb v diff [9] input differential voltage 400 v cc mv v ihhp highest input high voltage 1.2 v cc v v illp lowest input low voltage 0.0 v cc /2 v v comref [10] common mode range 1.0 v cc ? 1.2v v 3-level inputs v ihh three-level input high voltage min. v cc max. 0.87 * v cc v cc v v imm three-level input mid voltage min. v cc max. 0.47 * v cc 0.53 * v cc v v ill three-level input low voltage min. v cc max. 0.0 0.13 * v cc v i ihh input high current v in = v cc 200 a i imm input mid current v in = v cc /2 ?50 50 a i ill input low current v in = gnd ?200 a differential cml serial outputs: outa1 , outa2 , outb1 , outb2 , outc1 , outc2 , outd1 , outd2 v ohc output high voltage (v cc referenced) 100 ? differential load v cc ? 0.5 v cc ? 0.2 v 150 ? differential load v cc ? 0.5 v cc ? 0.2 v notes: 8. tested one output at a time , output shorted for less than one second, less than 10% duty cycle. 9. this is the minimum difference in voltage between the true and co mplement inputs required to ensure detection of a logic-1 or logic-0. a logic-1 exists when the true (+) input is more positive than the complement ( ? ) input. a logic-0 exists when the complement ( ? ) input is more positive than true (+) input. 10. the common mode range defines the allowable range of refclkb+ and refclkb ? when refclkb+ = refclkb ? . this marks the zero-crossing between the true and complement inputs as the signal switches between a logic-1 and a logic-0.
CYV15G0104TRB document #: 38-02100 rev. *b page 18 of 27 v olc output low voltage (v cc referenced) 100 ? differential load v cc ? 1.4 v cc ? 0.7 v 150 ? differential load v cc ? 1.4 v cc ? 0.7 v v odif output differential voltage |(out+) ? (out ? )| 100 ? differential load 450 900 mv 150 ? differential load 560 1000 mv differential serial line receiver inputs: ina1 , ina2 v diffs [9] input differential voltage |(in+) ? (in ? )| 100 1200 mv v ihe highest input high voltage v cc v v ile lowest input low voltage v cc ? 2.0 v i ihe input high current v in = v ihe max. 1350 a i ile input low current v in = v ile min. ?700 a vi com [11] common mode input range ((v cc ? 2.0v)+0.5)min, (v cc ? 0.5v) max. +1.25 +3.1 v power supply typ. max. i cc [12, 13] max power supply current refclkb = max commercial 585 690 ma i cc [12, 13] typical power supply current refclkb = 125 mhz commercial 560 660 ma CYV15G0104TRB dc electrical characteristics (continued) parameter description test conditions min. max. unit ac test loads and waveforms 2.0v 0.8v gnd 2.0v 0.8v 80% 20% 80% 20% r l (includes fixture and probe capacitance) 3.0v v th =1.4v 270 ps 270 ps [15] v th =1.4v 3.3v r1 r2 r1 = 590 ? r2 = 435 ? (includes fixture and probe capacitance) c l 7 pf (a) lvttl output test load r l = 100 ? (b) cml output test load c l (c) lvttl input test waveform (d) cml/lvpecl input test waveform 1ns 1 ns v ihe v ile v ihe v ile [14] [14] CYV15G0104TRB ac electrical characteristics parameter description min. max unit CYV15G0104TRB transmitter lvttl switching characteristics over the operating range f ts txclkb clock cycle frequency 19.5 150 mhz t txclk txclkb period=1/f ts 6.66 51.28 ns t txclkh [16] txclkb high time 2.2 ns t txclkl [16] txclkb low time 2.2 ns notes: 11. the common mode range defines the allowable range of input+ and input ? when input+ = input ? . this marks the zero-crossing between the true and complement inputs as the signal switches between a logic-1 and a logic-0. 12. maximum i cc is measured with v cc = max,t a = 25c, with all channels and serial line drivers e nabled, sending a continuous alternating 01 pattern, and outputs unloaded. 13. typical i cc is measured under similar conditions except with v cc = 3.3v, t a = 25c,with all channels enabled and one serial line driver per channel sending a continuous alternating 01 pattern. the redundant outputs on each channel are powered down and the parallel outputs are unload ed. 14. cypress uses constant current (ate) load configurations and forcing functions. this figure is for reference only. 15. the lvttl switching threshold is 1.4v. all timing references are made relative to where the signal edges cross the threshold voltage. 16. tested initially and after any design or process changes that may affect these parameters, but not 100% tested.
CYV15G0104TRB document #: 38-02100 rev. *b page 19 of 27 t txclkr [16, 17, 18, 19] txclkb rise time 0.2 1.7 ns t txclkf [16, 17, 18, 19] txclkb fall time 0.2 1.7 ns t txds transmit data set-up time to txclkb (txckselb = 0) 2.2 ns t txdh transmit data hold time from txclkb (txckselb = 0) 1.0 ns f tos txclkob clock frequency = 1x or 2x refclkb frequency 19.5 150 mhz t txclko txclkob period=1/f tos 6.66 51.28 ns t txclkod txclkob duty cycle centered at 60% high time ?1.9 0 ns CYV15G0104TRB receiver lvttl switching characteristics over the operating range f rs rxclka clock output frequency 9.75 150 mhz t rxclkp rxclka period = 1/f rs 6.66 102.56 ns t rxclkd rxclka duty cycle centered at 50% (full rate and half rate) ?1.0 +1.0 ns t rxclkr [16] rxclka rise time 0.3 1.2 ns t rxclkf [16] rxclka fall time 0.3 1.2 ns t rxdv? [20] status and data valid time to rxclka (rxratea = 0) (full rate) 5ui?2.0 [21] ns status and data valid time to rxclka (rxratea = 1) (half rate) 5ui?1.3 [21] ns t rxdv+ [20] status and data valid time to rxclka (rxratea = 0) 5ui?1.8 [21] ns status and data valid time to rxclka (rxratea = 1) 5ui?2.6 [21] ns f ros reclkoa clock frequency 19.5 150 mhz t reclko reclkoa period=1/f ros 6.66 51.28 ns t reclkod reclkoa duty cycle centered at 60% high time -1.9 0 ns CYV15G0104TRB refclkb switching characteristics over the operating range f ref refclkb clock frequency 19.5 150 mhz t refclk refclkb period = 1/f ref 6.6 51.28 ns t refh refclkb high time (txr ateb = 1)(half rate) 5.9 ns refclkb high time (txr ateb = 0)(full rate) 2.9 [16] ns t refl refclkb low time (txrateb = 1)(half rate) 5.9 ns refclkb low time (txrateb = 0)(full rate) 2.9 [16] ns t refd [22] refclkb duty cycle 30 70 % t refr [16, 17, 18, 19] refclkb rise time (20%?80%) 2 ns t reff [16, 17, 18, 19] refclkb fall time (20%?80%) 2 ns t trefds transmit data set-up time to refclkb - full rate (txrateb = 0, txckselb = 1) 2.4 ns transmit data set-up time to refclkb - half rate (txrateb = 1, txckselb = 1) 2.3 ns t trefdh transmit data hold time from refclkb - full rate (txrateb= 0, txckselb = 1) 1.0 ns transmit data hold time from refclkb - half rate (txrateb = 1, txckselb = 1) 1.6 ns CYV15G0104TRB trgclka switching characteristics over the operating range f trg trgclka clock frequency 19.5 150 mhz t refclk trgclka period = 1/f trg 6.6 51.28 ns notes: 17. the ratio of rise time to falling time must not vary by greater than 2:1. 18. for a given operating frequency, neither rise or fall specific ation can be greater than 20% of the clock-cycle period or the data sheet maximum time. 19. all transmit ac timing parameters measur ed with 1ns typical rise time and fall time. 20. parallel data output specifications are only valid if all outputs are loaded with similar dc and ac loads. 21. receiver ui (unit interval) is calculated as 1/(f trg * 20) (when trgratea = 1) or 1/(f trg * 10) (when trgratea = 0). in an operating link this is equivalent to t b . 22. the duty cycle specification is a simultaneous condition with the t refh and t refl parameters. this means that at faster character rates the refclkb duty cycle cannot be as large as 30%?70%. CYV15G0104TRB ac electrical characteristics (continued) parameter description min. max unit
CYV15G0104TRB document #: 38-02100 rev. *b page 20 of 27 t trgh trgclka high time (trgra tea = 1)(half rate) 5.9 ns trgclka high time (trgratea = 0)(full rate) 2.9 [16] ns t trgl trgclka low time (trgra tea = 1)(half rate) 5.9 ns trgclka low time (trgra tea = 0)(full rate) 2.9 [16] ns t trgd [23] trgclka duty cycle 30 70 % t trgr [16, 17, 18] trgclka rise time (20%?80%) 2 ns t trgf [16, 17, 18] trgclka fall time (20%?80%) 2 ns t trgrx [24] trgclka frequency referenced to received clock frequency ?0.15 +0.15 % CYV15G0104TRB bus configuration write timing characteristics over the operating range t datah bus configuration data hold 0 ns t datas bus configuration data setup 10 ns t wrenp bus configuration wren pulse width 10 ns CYV15G0104TRB jtag test clock characteristics over the operating range f tclk jtag test clock frequency 20 mhz t tclk jtag test clock period 50 ns CYV15G0104TRB device reset characteristics over the operating range t rst device reset pulse width 30 ns CYV15G0104TRB transmitter and reclo cker serial output characteristics over the operating range parameter description condition min. max. unit t b bit time 660 5128 ps t rise [16] cml output rise time 20 ? 80% (cml test load) spdselx = high 50 270 ps spdselx= mid 100 500 ps spdselx =low 180 1000 ps t fall [16] cml output fall time 80 ? 20% (cml test load) spdselx = high 50 270 ps spdselx = mid 100 500 ps spdselx =low 180 1000 ps pll characteristics parameter description condition min. typ. max. unit CYV15G0104TRB transmitter output pll characteristics t jtgensd [16, 25] transmit jitter generation - sd data rate refclkb = 27 mhz 200 ps t jtgenhd [16, 25] transmit jitter generation - hd data rate refclkb = 148.5 mhz 76 ps t txlock transmit pll lock to refclkb 200 s CYV15G0104TRB reclocker output pll characteristics t jrgensd [16, 26] reclocker jitter generation - sd data rate trgclka = 27 mhz 133 ps t jrgenhd [16, 26] reclocker jitter generation - hd data rate trgclka = 148.5 mhz 107 ps notes: 23. the duty cycle specification is a simultaneous condition with the t trgh and t trgl parameters. this means that at faster character rates the trgclka duty cycle cannot be as large as 30%?70%. 24. trgclka has no phase or frequency relationship with the recove red clock(s) and only acts as a centering reference to reduce clock synchronization time. trgclka must be within 1500 ppm ( 0.15%) of the transmitter pll reference (refclk) frequency. although transmitting to a hotlink ii receiver channel necessitates the frequency difference betw een the transmitter and receiver reference clocks to be within 1500-ppm, the stabili ty of the crystal needs to be within the limits specified by the appropriate standard when transmitting to a remote receiver that is compliant to that standa rd. 25. while sending bist data at the corresponding data rate, af ter 10,000 histogram hits, time referenced to refclkb input. 26. receiver input stream is bist data from the transmit channel . this data is reclocked and output to a wide-bandwidth digital sampling oscilloscope. the measurement was recorded after 10,000 histogram hits, time referenced to refclkb of the transmit channel. CYV15G0104TRB ac electrical characteristics (continued) parameter description min. max unit
CYV15G0104TRB document #: 38-02100 rev. *b page 21 of 27 CYV15G0104TRB receive pll characteristics over the operating range t rxlock receive pll lock to input data stream (cold start) 376k ui receive pll lock to input data stream 376k ui t rxunlock receive pll unlock rate 46 ui capacitance [16] parameter description test conditions max. unit c inttl ttl input capacitance t a = 25c, f 0 = 1 mhz, v cc = 3.3v 7 pf c inpecl pecl input capacitance t a = 25c, f 0 = 1 mhz, v cc = 3.3v 4 pf pll characteristics parameter description condition min. typ. max. unit CYV15G0104TRB hotlink ii transmitter switching waveforms note: 27. when refclkb is configured for half-rate operation (txrateb = 1) and data is captured using refclkb instead of a txclkb clo ck. data is captured using both the rising and falling edges of refclkb. txclkb txdb[9:0] t txdh t txds t txclk t txclkh t txclkl transmit interface write timing txclkb selected refclkb transmit interface t refclk t refh t refl t trefds t trefdh write timing txrateb = 0 txdb[ 9 :0] refclkb selected t trefdh transmit interface write timing txrateb = 1 refclkb t refclk t refl t refh note 27 t trefds t trefds t trefdh refclkb selected txdb[ 9 :0]
CYV15G0104TRB document #: 38-02100 rev. *b page 22 of 27 CYV15G0104TRB hotlink ii transmitter switching waveforms (continued) txclkob t txclko transmit interface txclkob timing txrate = 1 (internal) refclkb t refclk t refl t refh note 28 note 29 txclkob t txclko transmit interface txclkob timing refclkb note28 note29 t refclk t refh t refl txrateb = 0 switching waveforms for the CYV15G0104TRB hotlink ii receiver notes: 28. the txclkob output remains at the character rate regardless of the state of txrateb and does not follow the duty cycle of re fclkb. 29. the rising edge of txclkob output has no direct phase relationship to the refclkb input. rxclka+ rxda[9:0] t rxdv+ t rxclkp receive interface read timing rxclka? t rxdv ? rxratea = 0
CYV15G0104TRB document #: 38-02100 rev. *b page 23 of 27 switching waveforms for the CYV15G0104TRB hotlink ii receiver rxclka+ rxda[9:0] t rxdv+ t rxdv ? t rxclkp receive interface read timing rxclka? rxratea = 1 addr[2:0] t datas bus configuration write timing data[6:0] wren t datah t wrenp
CYV15G0104TRB document #: 38-02100 rev. *b page 24 of 27 table 7. package coordinate signal allocation ball id signal name signal type ball id signal name signal type ball id signal name signal type a01 nc no connect c07 nc no connect f17 vcc power a02 nc no connect c08 gnd ground f18 nc no connect a03 nc no connect c09 data[6] lvttl in pu f19 nc no connect a04 nc no connect c10 data[4] lvttl in pu f20 nc no connect a05 vcc power c11 data[2] lvttl in pu g01 gnd ground a06 nc no connect c12 data[0] lvttl in pu g02 wren lvttl in pu a07 toutb1? cml out c13 gnd ground g03 gnd ground a08 gnd ground c14 nc no connect g04 gnd ground a09 gnd ground c15 spdselb 3 -level sel g17 nc no connect a10 toutb2? cml out c16 vcc power g18 nc no connect a11 ina1? cml in c17 ldtden lvttl in pu g19 spdsela 3-level sel a12 routa1? cml out c18 trst lvttl in pu g20 nc no connect a13 gnd ground c19 gnd ground h01 gnd ground a14 ina2? cml in c20 tdo lvttl 3-s out h02 gnd ground a15 routa2? cml out d01 tclk lvttl in pd h03 gnd ground a16 vcc power d02 reset lvttl in pu h04 gnd ground a17 vcc power d03 vcc power h17 gnd ground a18 nc no connect d04 insela lvttl in h18 gnd ground a19 vcc power d05 vcc power h19 gnd ground a20 nc no connect d06 ulca lvttl in pu h20 gnd ground b01 vcc power d07 nc no connect j01 gnd ground b02 nc no connect d08 gnd ground j02 gnd ground b03 vcc power d09 data[5] lvttl in pu j03 gnd ground b04 nc no connect d10 data[3] lvttl in pu j04 gnd ground b05 vcc power d11 data[1] lvttl in pu j17 nc no connect b06 vcc power d12 gnd ground j18 nc no connect b07 toutb1+ cml out d13 gnd ground j19 nc no connect b08 gnd ground d14 gnd ground j20 nc no connect b09 nc no connect d15 nc no connect k01 nc no connect b10 toutb2+ cml out d16 vc c power k02 nc no connect b11 ina1+ cml in d17 nc no connect k03 gnd ground b12 routa1+ cml out d18 vcc power k04 gnd ground b13 gnd ground d19 scanen2 lvttl in pd k17 nc no connect b14 ina2+ cml in d20 tmen3 lvttl in pd k18 nc no connect b15 routa2+ cml out e01 vcc power k19 nc no connect b16 vcc power e02 vcc power k20 nc no connect b17 nc no connect e03 vcc power l01 nc no connect b18 nc no connect e04 vcc power l02 nc no connect b19 nc no connect e17 vcc power l03 nc no connect b20 nc no connect e18 vcc power l04 gnd ground c01 tdi lvttl in pu e19 vcc power l17 nc no connect c02 tms lvttl in pu e20 vcc power l18 nc no connect c03 vcc power f01 nc no connect l19 nc no connect
CYV15G0104TRB document #: 38-02100 rev. *b page 25 of 27 c04 vcc power f02 nc no connect l20 gnd ground c05 vcc power f03 vcc power m01 nc no connect c06 nc no connect f04 nc no connect m02 nc no connect m03 nc no connect u03 txdb[2] lvttl in w03 nc no connect m04 nc no connect u04 txdb[9] lvttl in w04 nc no connect m17 nc no connect u05 vcc power w05 vcc power m18 nc no connect u06 nc no connect w06 nc no connect m19 nc no connect u07 nc no connect w07 nc no connect m20 gnd ground u08 gnd ground w08 gnd ground n01 gnd ground u09 gnd ground w09 addr [2] lvttl in pu n02 gnd ground u10 addr [0] lvttl in pu w10 addr [1] lvttl in pu n03 gnd ground u11 refclkb? pecl in w11 rxclka+ lvttl out n04 gnd ground u12 gnd ground w12 repdoa lvttl out n17 gnd ground u13 gnd ground w13 gnd ground n18 gnd ground u14 gnd ground w14 gnd ground n19 gnd ground u15 vcc power w15 vcc power n20 gnd ground u16 vcc power w16 vcc power p01 nc no connect u17 rxda[4] lvttl out w17 lfia lvttl out p02 nc no connect u18 vcc power w18 trgclka+ pecl in p03 nc no connect u19 biststa lvttl out w19 rxda[6] lvttl out p04 nc no connect u20 rxda[0] lvttl out w20 rxda[3] lvttl out p17 gnd ground v01 txdb[3] lvttl in y01 txdb[6] lvttl in p18 gnd ground v02 txdb[4] lvttl in y02 txclkb lvttl in pd p19 gnd ground v03 txdb[8] lvttl in y03 nc no connect p20 gnd ground v04 nc no connect y04 nc no connect r01 nc no connect v05 vcc power y05 vcc power r02 nc no connect v06 nc no connect y06 nc no connect r03 nc no connect v07 nc no connect y07 nc no connect r04 nc no connect v08 gnd ground y08 gnd ground r17 vcc power v09 nc no connect y09 txclkob lvttl out r18 vcc power v10 gnd ground y10 nc no connect r19 vcc power v11 refclkb+ pecl in y11 gnd ground r20 vcc power v12 reclkoa lvttl out y12 rxclka? lvttl out t01 vcc power v13 gnd ground y13 gnd ground t02 vcc power v14 gnd ground y14 gnd ground t03 vcc power v15 vcc power y15 vcc power t04 vcc power v16 vcc power y16 vcc power t17 vcc power v17 rxda[9] lvttl out y17 txerrb lvttl out t18 vcc power v18 rxda[5] lvttl out y18 trgclka? pecl in t19 vcc power v19 rxda[2] lvttl out y19 rxda[8] lvttl out t20 vcc power v20 rxda[1] lvttl out y20 rxda[7] lvttl out u01 txdb[0] lvttl in w01 txdb[5] lvttl in u02 txdb[1] lvttl in w02 txdb[7] lvttl in table 7. package coordinate signal allocation (continued) ball id signal name signal type ball id signal name signal type ball id signal name signal type
CYV15G0104TRB document #: 38-02100 rev. *b page 26 of 27 hotlink is a registered trademark and ho tlink ii is a trademark of cypress se miconductor. all product and company names mentioned in this document may be the trademarks of their respective holders. ordering information speed ordering code package name package type operating range standard CYV15G0104TRB-bgc bl256 256-ball thermally enhanced ball grid array commercial standard CYV15G0104TRB-bgxc bl256 pb-free 256-ball thermally enhanced ball grid array commercial package diagram 256-lead l2 ball grid array (27 x 27 x 1.57 mm) bl256 51-85123-*e
CYV15G0104TRB document #: 38-02100 rev. *b page 27 of 27 document history page document title: CYV15G0104TRB independent clock ho tlink ii? serializer and reclocking deserializer document number: 38-02100 rev. ecn no. issue date orig. of change description of change ** 244348 see ecn fre new data sheet *a 338721 see ecn sua added pb-free package option availability *b 384307 see ecn agt revised setup and hold times (t txdh , t trefds , t trefdh , t rxdv? , t rxdv+ )

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